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hm62w8511h series 4m high speed sram (512-kword 8-bit) ade-203-750d (z) rev. 1.0 sep. 15, 1998 description the hm62w8511h is a 4-mbit high speed static ram organized 512-kword 8-bit. it has realized high speed access time by employing cmos process (4-transistor + 2-poly resistor memory cell) and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. the hm62w8511h is packaged in 400-mil 36-pin soj for high density surface mounting. features single supply : 3.3 v 0.3 v access time 12/15 ns (max) completely static memory ? no clock or timing strobe required equal access and cycle times directly ttl compatible ? all inputs and outputs operating current : 150/130 ma (max) ttl standby current : 60/50 ma (max) cmos standby current : 5 ma (max) : 1 ma (max) (l-version) data retension current : 0.6 ma (max) (l-version) data retension voltage : 2 v (min) (l-version) center v cc and v ss type pinout
hm62w8511h series 2 ordering information type no. access time package hm62w8511hjp-12 hm62w8511hjp-15 12 ns 15 ns 400-mil 36-pin plastic soj (cp-36d) hm62w8511hljp-12 hm62w8511hljp-15 12 ns 15 ns pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a0 a1 a2 a3 a4 cs i/o1 i/o2 v cc v ss i/o3 i/o4 we a5 a6 a7 a8 a9 nc a18 a17 a16 a15 oe i/o8 i/o7 v ss v cc i/o6 i/o5 a14 a13 a12 a11 a10 nc (top view) hm62w8511hjp/hljp series
hm62w8511h series 3 pin description pin name function a0 to a18 address input i/o1 to i/o8 data input/output cs chip select oe output enable we write enable v cc power supply v ss ground nc no connection block diagram i/o1 . . . i/o8 we input data control column i/o column decoder memory matrix 256 rows 8 columns 256 blocks 8 bit (4,194,304 bits) row decoder oe cs cs cs v cc v ss cs a1 a17 a7 a11 a16 a2 a6 a5 a10 a8 a9 a12 a13 a14 a0 a18 a15 a3 a4 (lsb) (msb) (lsb) (msb)
hm62w8511h series 4 operation table cs oe we mode v cc current i/o ref. cycle h standby i sb , i sb1 high-z l h h output disable i cc high-z l l h read i cc dout read cycle (1) to (3) l h l write i cc din write cycle (1) l l l write i cc din write cycle (2) note: : h or l absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ?.5 to +4.6 v voltage on any pin relative to v ss v t ?.5* 1 to v cc +0.5* 2 v power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg ?5 to +125 c storage temperature under bias tbias ?0 to +85 c notes: 1. v t (min) = ?.0 v for pulse width (under shoot) 8 ns 2. v t (max) = v cc +2.0 v for pulse width (over shoot) 8 ns recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc * 3 3.0 3.3 3.6 v v ss * 4 000v input voltage v ih 2.2 v cc + 0.5* 2 v v il ?.5* 1 0.8 v notes: 1. v il (min) = ?.0 v for pulse width (under shoot) 8 ns 2. v ih (max) = v cc +2.0 v for pulse width (over shoot) 8 ns 3. the supply voltage with all v cc pins must be on the same level. 4. the supply voltage with all v ss pins must be on the same level.
hm62w8511h series 5 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0v) parameter symbol min typ* 1 max unit test conditions input leakage current ii li i2 m a vin = v ss to v cc output leakage current ii lo i2 m a vin = v ss to v cc operation power supply current 12 ns cycle i cc 150 ma min cycle cs = v il , lout = 0 ma other inputs = v ih /v il 15 ns cycle i cc 130 standby power supply current 12 ns cycle i sb 60 ma min cycle cs = v ih , other inputs = v ih /v il 15 ns cycle i sb 50 i sb1 0.05 5 ma f = 0 mhz v cc 3 cs 3 v cc - 0.2 v, (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc - 0.2 v ? 2 0.05* 2 1.0* 2 output voltage v ol 0.4 v i ol = 8 ma v oh 2.4 v i oh = ? ma notes: 1. typical values are at v cc = 3.3 v, ta = +25 c and not guaranteed. 2. this characteristics is guaranteed only for l-version. capacitance (ta = +25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions input capacitance* 1 cin 6 pf vin = 0 v input/output capacitance* 1 c i/o 8 pfv i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm62w8511h series 6 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, unless otherwise noted.) test conditions input pulse levels: 3.0 v/0.0 v input rise and fall time: 3 ns input and output timing reference levels: 1.5 v output load: see figures (including scope and jig) dout 353 w 319 w 3.3 v 5 pf output load (b) (for t clz , t olz , t chz , t ohz , t whz , and t ow ) dout rl=50 w output load (a) 1.5 v zo=50 w read cycle hm62w8511h -12 -15 parameter symbol min max min max unit notes read cycle time t rc 12 15 ns address access time t aa 12 15 ns chip select access time t acs 12 15 ns output enable to outpput valid t oe ? ? ns output hold from address change t oh 33ns chip select to output in low-z t clz 33ns1 output enable to output in low-z t olz 00ns1 chip deselect to output in high-z t chz ? ? ns1 output disable to output in high-z t ohz ? ? ns1
hm62w8511h series 7 write cycle hm62w8511h -12 -15 parameter symbol min max min max unit notes write cycle time t wc 12 15 ns address valid to end of write t aw 8 10 ns chip select to end of write t cw 810ns9 write pulse width t wp 810ns8 address setup time t as 00ns6 write recovery time t wr 00ns7 data to write time overlap t dw 67ns data hold from write time t dh 00ns write disable to output in low-z t ow 33ns1 output disable to output in high-z t ohz ? ? ns1 write enable to output in high-z t whz ? ? ns1 note: 1. transition is measured 200 mv from steady voltage with load (b). this parameter is sampled and not 100% tested. 2. address should be valid prior to or coincident with cs transition low. 3. we and/or cs must be high during address transition time. 4. if cs and oe are low during this period, i/o pins are in the output state. then, the data input signals of opposite phase to the outputs must not be applied to them. 5. if the cs low transition occurs simultaneously with the we low transition or after the we transition, output remains a high impedance state. 6. t as is measured from the latest address transition to the later of cs or we going low. 7. t wr is measured from the earlier of cs or we going high to the first address transition. 8. a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low. a write ends at the earliest transition among cs going high and we going high. t wp is measured from the beginnig of write to the end of write. 9. t cw is measured from the later of cs going low to the the end of write.
hm62w8511h series 8 timing waveforms read timing waveform (1) ( we = v ih ) t aa t acs t rc t oe t clz valid data address cs dout valid address high impedance t ohz oe t oh t chz t olz read timing waveform (2) ( we = v ih , cs = v il , oe = v il ) t aa t rc valid data address dout valid address t oh t oh
hm62w8511h series 9 read timing waveform (3) ( we = v ih , cs = v il , oe = v il )* 2 valid data cs dout high impedance high impedance t clz t acs t rc t chz write timing waveform (1) ( we controlled) address we * 3 dout din t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs * 3 t ohz * 4 * 4 oe high impedance* 5
hm62w8511h series 10 write timing waveform (2) ( cs controlled) address we * 3 dout din t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs * 3 t whz t ow * 4 * 4 high impedance* 5
hm62w8511h series 11 low v cc data retention characteristics (ta = 0 to +70 c) this characteristics is guaranteed only for l-version. parameter symbol min typ* 1 max unit test conditions v cc for data retention v dr 2.0 v v cc 3 cs 3 v cc ?0.2 v (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc ?0.2 v data retention current i ccdr 40 600 m av cc = 3 v, v cc 3 cs 3 v cc ?0.2 v (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc ?0.2 v chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r 5 ms note: 1. typical values are at v cc = 3.0 v, ta = +25?c, and not guaranteed. low v cc data retention timing waveform v cc 3.0 v 2.2 v 0 v cs t cdr t r v cc 3 cs 3 v cc ?0.2 v v dr data retention mode
hm62w8511h series 12 package dimensions hm62w8511hjp/hljp series (cp-36d) 9.40 0.25 1 18 0.43 0.10 3.50 0.26 19 36 23.62 max 23.25 0.74 10.16 0.13 11.18 0.13 1.30 max 2.85 0.12 0.10 1.27 0.80 +0.25 ?.17 hitachi code jedec eiaj weight (reference value) cp-36d conforms conforms 1.4 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension
hm62w8511h series 13 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca 94005-1897 tel: <1> (800) 285-1601 fax: <1> (303) 297-0447 for further information write to:

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